Design-Reuse

Momentum Grows With Introduction of DFI Specification Version 2.0

PALO ALTO, Calif., February 08, 2008 — Denali Software, Inc., today, on behalf of all DDR PHY Interface (DFI) specification participating members, including representatives from industry-leading ...
EDN

Overcoming DDR-2-interface challenges

DDR (double-data-rate) memory devices do an admirable job of unclogging the memory bottleneck between external memory and ASICs, but the nature of DDR is stretching the skills of designers creating ...
Design-Reuse

Core-assisted approach accelerates debug of FPGA DDR II interfaces

With IO rates of several hundred megahertz, FPGAs have become an excellent medium for implementation of high-speed memory controllers. Fast memory storage and retrieval often involve implementing DDR ...
EDN

ESC – New Synopsys Universal DDR Controllers Improve Performance and Reduce Cost of Embedded DRAM Interfaces

Mountain View, Calif. – Synopsys, Inc. today announced the availability of the high-performance DesignWare Universal DDR Protocol and Memory Controllers, both supporting the DDR2, DDR3, Mobile DDR and ...