EDN

Model generator supports leading memory makers

BANGALORE, India — Chip design services provider eInfochips has unveiled a memory model generator based on the DDR2 SDRAM SystemVerilog Verification Methodology Manual approach. The tool will generate ...
Design-Reuse

eInfochips announces DDR2 SDRAM SystemVerilog & VMM based Memory Model Generator Tool

GUI based tool targeted to reduce verification time and maximize memory coverage Ahmedabad -- June 2, 2009 -- eInfochips, Inc., a leading IP driven ASIC/FPGA/SoC, Embedded Systems & Software design ...
Electronic Design

Generator Delivers Multiport Embedded Memory Designs

Memoir Systems announced their Algorithmic memory awhile ago but its use required a custom design (see Algorithmic Memory Simplifies SoC Memory Subsystem Design). The idea was to take standard single ...
EDN

Maximize a waveform generator’s memory

The architecture of an AWG (arbitrary waveform generator) looks like that of a DSO (digital storage oscilloscope) in reverse. Waveform memory plays a critical role in both instruments. DSOs capture ...